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here has been considerable human effort into attaining low distortion in amplifiers of many applications at all frequencies. In 1950, the best audio power amplifiers produced distortion of about 0.1% at 1 kHz, and in the 1990s, this has been reduced to about 0.001% at 1 kHz, and about 0.02% at 20 kHz, although one manufacturer claims 0.0025% at 20 kHz.

 

The vast majority of commercial audio amplifiers more or less follow well established standard designs.

 

There are some exceptions: a Technics SE-A1 amplifier which is known of in some countries incorporates an A-class output stage supplied by a floating low voltage high current power supply. This power supply is connected to a B-class high voltage output stage.

 

An LT1166 integrated circuit is primarily intended to control the quiescent bias feeding output transistors in audio amplifiers. The LT1166 consists of a low gain transconductance differential amplifier (gain of 0.125 mho) with an inverting and a non-inverting input. The circuitry has a local negative feedback path connecting an output of the power stage to the inverting input of the transconductance amplifier. The input of the output stage is the non-inverting input of the transconductance amplifier. Two local dominant poles necessary for stability are formed by the use of shunt capacitors to ground from the transconductance amplifier's outputs. The Linear Technology application circuitry promises distortions no better than many commercial products.

 

In the Journal of Audio Engineering Society, vol 29, no 1/2, January/February 1981, pages 27-30, M. J. Hawksford, discloses as a mere paper publication a theoretical means of cancelling distortion in any amplifier stage, including an output stage. This is achieved by subtracting the signals feeding the output power transistors inputs from the amplifier output, and then adding this signal back into the signal driving the output transistors'inputs.

 

Iwamatsu in U.S. Pat. No. 4,476,442 again as a mere paper publication disclosed circuitry based on the principles of Hawksford. In one embodiment described in this patent specification, Iwamatsu discloses floating power supplies supplying the adding and subtracting circuitry. These floating supplies follow a voltage equal to the sum of the output signal plus a signal linearly proportional to current flowing through an output load. However, Iwamatsu's circuits do not include local dominant poles.

 

Robert R. Cordell in "MOSPOWER APPLICATIONS", Siliconix inc. ISBN 0930519-000, 1984, 6.6.3 discloses an audio power amplifier essentially the same as one of the Hawksford's circuits, but including local dominant poles required for stability. This circuit has however no provision for thermal stability, nor floating power supply rails.

 

The current inventor Bruce H Candy previously in U.S. Pat. No. 5,892,398 as a paper publication only, disclosed an amplifier also utilising the principles of Hawksford, but including local dominant poles required for stability, thermal tracking circuitry for thermal stability, floating power supplies which track the output signal, rather than to the sum of the output signal plus a signal linearly proportional to the current flowing through the output load as in the case of Iwamatsu. Candy also disclosed an output stage input current source load which is also supplied by power from the floating power supplies. It was possible with such an arrangement according to my experiments which were not published to attain a distortion in the order of only 1 part per million at 20 kHz at several hundred watts of output.

 

Williamson et al. In U.S. Pat. No. 5,396,194 describes as a mere paper publication a switch mode amplifier containing floating low voltage high current power supplies which supply an A-class amplifier. This is similar to the technics SE-A1 except that the drive circuitry is switch-mode rather than class-B and that the power supplying the A-class amplifier is derived from the switch mode power supply rather than a separate power supply.

 

In one of the Williamson paper descriptions there was described floating power supplies to supply small signal operational amplifiers which were connected as servo loops to control the current flowing through the output devices. There are two feedback paths containing a capacitor which form two local dominant poles which are essential for stability.

 

The current inventor Bruce H Candy in U.S. patent application 09/054070 describes an amplifier consisting of at least one operational amplifier, a first error correction amplifier, connected up as a servo loop to control the output voltage, as opposed to the output current as in the case of Williamson et al. These operational amplifiers are supplied by power from floating power supplies which track the output voltage.

 

Candy further describes a local dominant pole required for stability, and the advantages of using wide band operational amplifiers, with gain bandwidth products of more than 100 MHz. In addition, I described a second error correction amplifier, consisting of another operational amplifier, also preferably wideband, connected up as a servo loop to control the output voltage stage which includes the first error correction amplifier. In other words, I described a 2nd order local dominant pole formed by the signal path being amplified by two error correction stages in series.

 

This also is supplied by the floating power supplies. I further described the advantages of implementing high gain stages with local negative feedback and the attendant local dominant poles required for stability in other stages of the amplifier to reduce distortion. This arrangement does not require the precise setting of the adding and subtracting electronics disclosed by Hawksford and related circuits.

 

Audio power amplifiers, or operational amplifiers, Usually consist of three definable stages, an input stage, voltage amplifier stage and output stage. In power amplifiers, the output stage, sometimes called the power output stage, usually produces most distortion. However, the distortion of the power output stage maybe substantially reduced by some of the concepts described herein.

 

Compared to these distortion reduced power output stages, the lowest distortion conventional input stages, voltage amplifier stages may produce substantially greater distortion.

 

Conventional low distortion input stages are usually a differential voltage to current converter which produce a differential output current. In these low distortion traditional architectures, the differential current output of this input stage is connected to a current mirror, and the output node of the differential current output of the input stage and current mirror is connected to a common emitter cascode amplifier; said common emitter amplifier sometimes being a Darlington. The amplifier's dominant pole is set by a network including a capacitor connected between the output and input of this common emitter cascode stage. Details of these stages are described in a review by Douglas Self in a series of articles in "Electronics World+Wireless World" from August 1993 to January 1994, and also in his book, ISBN 0-7506-2788-3, "Audio power amplifier design handbook", Newness, Reprinted 1997/1998, and the second edition ISBN 0 7506 4527 X, 2000. Another review is given by Ben Duncan, High Performance Audio Power Amplifiers, ISBN 0 7506 2629 1, Newness 1996.

 

An object of this invention is to provide a further circuit arrangement which assists in construction of even more accurate amplifiers or at the least, provides the public with a useful alternative.

 

DISCLOSURE OF THE INVENTION

 

In one form of this invention although this may not be the only or indeed the broadest form of this there is proposed an electronic amplifier having an input, and an output, and including an output stage containing output transistors being connected to the amplifier output,

 

the output stage including an output error correction stage containing a first amplifier and a second amplifier, an input to the output stage being connected to an input of the first amplifier,

 

wherein there are at least four local negative feedback paths,

 

a first local negative feedback path being between an output of the output stage and an input of the first amplifier,

 

a second local negative path being between an output of the first amplifier and an input of the first amplifier,

 

and a third local negative feedback path being between an output of the output stage and an input of the second amplifier,

 

and a fourth local negative path being between an output of the second amplifier and an input of the second amplifier,

 

an output of the first amplifier being connected to an input of output stage transistor buffers or output stage transistors through a first network,

 

an output of the second amplifier being connected to an input of output stage transistor buffers or output stage transistors through a second network,

 

such that the first network transfers high frequencies from the first amplifier to an input of output stage transistor buffers or output stage transistors more substantially than the second network, and the second network transfers low frequencies from the second amplifier to the to an input of output stage transistor buffers or output stage transistors more substantially than the first network, such that components of the first and second amplifier, first, second, third and fourth local negative feedback paths, first and second networks, and

 

output transistors and output stage transistor buffers, are selected to form a substantially second order local dominant pole,

 

and the amplifier having it's input connected to an amplifier input stage,

 

wherein the input stage may include a current mirror and a voltage amplification stage, an output of the amplifier input stage being connected to the input of the output stage,

 

and the first and the second amplifier being supplied by power from a floating power supply means coupled to either an or the output of the output stage so that a voltage of floating power supply supplying the first amplifier and second amplifier will follow substantially an output voltage of the output stage.

 

Other embodiments of the invention are as defined in the attached claims.

 

In one preferred embodiment, the output stage contains two error correcting servo loops, a first and a second error correcting servo loop.

 

The first error correcting servo loop includes a first electronic amplifier, preferably a wideband amplifier, with an inverting and a non-inverting input.

 

The second error correcting servo loop includes a second electronic amplifier, preferably a wideband amplifier, with an inverting and a non-inverting input.

 

A first local negative feedback path connects an output of the amplifier to the inverting input of the first amplifier.

 

A second local negative feedback path is connected between the output of the first amplifier and it's inverting input; the negative feedback path includes at least one capacitor, together with the first electronic amplifier set with a local dominant pole.

 

A third local negative feedback path connects an output of the amplifier to the inverting input of the second amplifier.

 

A fourth local negative feedback path is connected between the output of the second amplifier and it's inverting input, which includes at least one capacitor, a second capacitor. The input to the error correction electronics, and thus the output stage, is at the first amplifier's non-inverting input. The output of the first amplifier is connected to the second amplifier's non-inverting input and to the input of the output transistors, or to the inputs of buffer amplifiers feeding the output transistors, via a first path including a first network, consisting of a high pass filter containing at least one capacitor, a third capacitor. The output of the second amplifier is connected to the input of the output transistors, or to the inputs of buffer amplifiers feeding the output transistors, via a second path including a second network which includes at least one resistor. The first path passes mostly, or only, high frequency signals to the inputs of the output transistors, or to the inputs of buffer amplifiers feeding the output transistors. The second path passes mostly or only lower frequency signals, including direct current signals, to the inputs of the output transistors, or to the inputs of buffer amplifiers feeding the output transistors. The components of the first and second amplifier, first, second, third and fourth local negative feedback paths, first and second networks, and output transistors and output stage transistor buffers, are selected to form a substantially second lower order local dominant pole. The power supplies supplying the first and second error correcting servo loops, consisting of the first and second amplifiers, first and second networks, first and second paths and first through to fourth local negative feedback paths, are floating power supplies which substantially track the amplifier's output signal. Thus high frequency stability of the output stage is mostly determined by the first electronic amplifier and the first local dominant pole, and thus high frequency stability is relatively independent of the second electronic amplifier with it's second local dominant pole. Thus the combination of the first and second error correcting servo loops creates a 2nd order local dominant pole as does the disclosure of Candy in U.S. patent application 09/054070, but herein the high frequency path does not include the second electronic amplifier as does the amplifier disclosed by Candy.

 

In order to successfully apply a reasonable amount of global negative feedback to the whole amplifier, and local negative feedback to the first and second error correcting servo loops, whilst maintaining a safe margin of stability, the frequency at which the closed loop phase shift exceeds 90 degrees of the whole output stage including the error correcting servo loops, should remain similar to that intrinsic to the output power transistors plus their buffers. Typical complementary voltage follower power MOSFET stages have useful responses up to a few MHz for unconditional stability. Above this frequency, the phase shift can substantially exceed 90 degrees, in which case at these frequencies, the open loop gain of any servo loop about which negative feedback is to be applied should be of the order of unity. Thus, the amplifiers employed in these servo loops should have gain-bandwidth products substantially more than a few MHz so that the intrinsic closed loop phase shifts of these amplifiers add little to the total phase shift. As "video" or "wideband" operational amplifiers are now of low cost and common, these are suitable.

 

In the simplest case where the first local negative feedback path consists of a resistor, say 470 ohms, and the third local negative feedback path likewise, and the second local negative feedback path consists of a capacitor, say 150 pF, and the fourth local negative feedback path likewise, but 1 nF, and the first path first network) consists of a capacitor of say 2.2 nF, and the second path (second network) consists of a resistor of say 220 ohms, with the second and fourth local negative feedback paths closed, but the first and third open, the open loop gain of the servo loops at a few MHz is of the order of 1, and the amount of negative feedback at 20 kHz is a couple of thousand times. Thus the reduction in distortion of this stage may be three orders of magnitude.

 

In accordance with the teaching of this invention, an amplifier has been built that produces distortion harmonics to a 20 kHz sinewave of a few hundred parts per billion, that is of the order of -130 dB at several hundred watts output power.

 

The advantages of this arrangement compared to the arrangement disclosed by the current inventor Candy in U.S. patent application 09/054070 is two fold.

 

First, the phase shift at high frequencies is less, and hence, more global or local feedback may be applied. Second, the second electronic operational amplifier may have a more relaxed high frequency specification because the high frequency response delay is set by the lower supply voltage first operational amplifier, and the higher open loop gain operational amplifiers are more readily available with more relaxed high frequency specifications.

 

This error corrected output stage may produce substantially less distortion than conventional input stages and voltage amplifier stages. Hence to take full advantage of the low distortion of the error-corrected output stage disclosed herein, the other stages also need to be improved upon.

 

These stages may be substantially improved by the application of additional servo loops and local dominant poles forming networks required for stability. In particular, the distortion generated by conventional current mirrors and the voltage amplifier may be substantially reduced by local negative feedback.

 

A very low distortion current mirror may be implemented by passing the controlling current through a third resistor, across which a potential difference occurs according to Ohm's law. This voltage is then fed to a high input impedance voltage to current converter. For example, the resistor through which the control current flows is connected to a first power supply. The input current end of this first resistor is connected to a non-inverting input of an operational amplifier. The operational amplifier's output is fed to the control input of a transistor, preferably being a very low capacitance type with high gain. Two small signal wideband (RF) bipolar devices connected as a Darlington pair are suitable, with the input base as said input. The output emitter of this pair is connected to a fourth resistor and to the inverting input of said operational amplifier. The other end of the fourth resistor is connected to the first power supply. The collector outputs of the Darlington pair produces a current accurately in proportion to the first and second resistor ratio and in proportion to the control current. Note there is a high degree of local negative feedback. Assuming the operational amplifier is unity gain stable, then the local dominant pole required for stability is built within the operational amplifier. If said operational amplifier is a wide-band device, then the phase lag at high frequency will be relatively small, and thus have no substantial effect on the stability requirements of the amplifiers overall negative feedback. The recommended low capacitance requirement of the wideband Darlington will ensure minimal variable capacitance distortion as a function of variable voltage at high frequency.

 

A very low distortion voltage amplifier stage with a very high impedance virtual earth input may be implemented using high open loop gain local negative feedback with attendant local poles required for stability. For example, two amplifiers may be connected within the voltage amplifier stage, one may be used to correct for the base-emitter non-linearities of the voltage amplifier stage amplifying transistors, that is to ensure an accurate voltage to current conversion, and the other may be used both to increase the lower frequency open loop gain and also to implement a high input impedance.

 

In all three areas of substantially improved accuracy described herein, namely the power output stage, the current mirror and voltage amplifier stage, the closed loop phase shift at high frequency is approximately unchanged, but the distortion greatly improved compared to the conventional art. This is achieved by employing wideband-gain components with substantial local negative feedback whilst attaining stability by the implementation of local dominant pole forming networks. In each case, the local negative feedback corrects for nonlinearities of local transistors without affecting the intrinsic closed loop gain and phase shift of the stage, that is the closed loop gain/phase shift without the error correction electronics connected into the circuitry.

 

The above and below descriptions describe amplifier circuitry which is not symmetrical relative to the positive and negative power supply rails. This is for simplicity, and the same basic description could equally be applied to more or fully symmetric circuitry.

 

BRIEF DESCRIPTION OF THE DRAWINGS

 

For a better understanding of this invention it will now be described with reference to preferred embodiments which are described hereinafter with reference to drawings wherein

 

FIG. 1 shows for the embodiment incorporating this invention, a second order local dominant pole output stage error correction electronic schematic, including separated high and low frequency signal paths,

 

FIG. 2 shows for the same embodiment, an amplifier input stage, a low distortion current mirror, including a local feedback path and associated local dominant pole, and a low distortion voltage amplifying stage which includes a local dominant pole forming network,

 

FIG. 3 for the same embodiment, three complementary identical parallel power output pairs are shown.

 

Referring to FIG. 1, the input to this output stage error correction electronic schematic, the input to the output stage 70 is connected to a constant current source 71, which provides the quiescent current to voltage amplifying stage, and 70 is also connected to an input of the first error correcting servo loop, namely the non-inverting input of the first electronic amplifier 103. 71 is unnecessary if the voltage amplifying stage is symmetrical relative to the supply rails. 70 is connected to 103 via a small valued resistor 102 inserted for very high frequency stability purposes. 71 is connected to a first floating power supply, namely, a positive voltage rail 100 whose voltage follows the output rail voltage on output signal rail 18. The positive power supply pin of 103 is connected to an output 104 of a linear voltage regulator 112. The input of 112 is fed from the positive floating power rail 100.

 

The reference "ground" pin of 112 is connected to the output signal rail 18. The negative power supply pin of 103 is connected to an output 105 of a linear voltage regulator 113. The input of 113 is fed from a negative floating power rail 101. The reference "ground" pin of 113 is connected to the output signal rail 18. Capacitors 107 and 106 a.c. couple 104 to 18 and capacitors 108 and 109 a.c couple 105 to 18. A first local feedback path connects amplifier output 18 to the first electronic amplifier 103 by means of the connection between 18 and the inverting input of 103 via resistor 111. A second local feedback path connects the output of the first electronic amplifier 103 and it's inverting input by a network which is simply capacitor 110 in this embodiment.

 

The values of 111 and 110 and the gain of 103 partly define the second order local dominant pole. A high frequency path, consisting of a first network consisting of resistor 121 and series capacitor 124 which connects the output of 103 to an input node 150 of N-channel output FET buffer stages consisting of amplifiers 200, 220, and 240. 121 is a small valued resistor inserted for very high frequency stability purposes. The node connecting 121 to 124 also is connected to an input of a second electronic amplifier 123, namely to its non-inverting input. This connection is made via a small valued resistor 122 inserted for very high frequency stability purposes. The positive power supply pin of 123 is connected to positive floating power rail 100. The negative power supply pin of 123 is connected to negative floating power rail 101. Capacitor 184 a.c. couples 100 to 18 and capacitor 185 a.c couples 101 to 18. A third local feedback path connects the amplifier output 18 to the second electronic amplifier 123 by means of the connection between 18 and the inverting input of 103 via resistor 126. A fourth local feedback path connects the output of the second electronic amplifier 123 and it's inverting input via a network which in this preferred embodiment consists of capacitor 125. A second network consisting of resistor 190 connects a low frequency path between the output of 123 and the input node 150 of the N-channel output FET transistor buffers. It is assumed that 121 is substantially less in value than 190. The values of 111, 110, 121, 124, 125, 126, 190 and the gains of 103 and 123 together with the output transistors and output transistor buffers define the second order local dominant pole of this output stage error correction electronic schematic. The node 150 connecting 190, 124 and the inputs of the N-channel output FET buffers, is also connected to resistor 127 and parallel capacitor 131. A node 151 which joins 127 and 131 at their other ends is connected P-channel output FET buffers 210, 230, 250. This node 151 is also connected to a constant current source 128 which is connected to negative floating power rail 101. The current flowing out of 128 may be a function of power output transistor temperature so that the output transistor quiescent current may be held approximately temperature independent. Capacitor 180 a.c. couples 100 to 18 and capacitor 181 a.c. couples 101 to 18.

 

The anode of Zener diode 164 is connected to 18, while its cathode is connected to the emitter of npn transistor 165 and resistor 167. The cathode of diode 168 is connected to 100 while its anode is connected to 167 and the base of 165 and to resistor 162 and to the anode of zener diode 166. The collector of 165 is connected to resistor 163, the cathode of 166 and the gate of N-channel FET 161. The source of 161 is connected to 162 and its drain is connected to a positive power supply rail 160. Resistor 163 is also connected to 160. 161, 162, 163, 164, 165, 166, 167, and 168 form a positive linear regulator which defines the voltage floating positive rail voltage 100.

 

The cathode of Zener diode 173 is connected to 18, while its anode is connected to the emitter of pnp transistor 172 and resistor 177. The anode of diode 176 is connected to 101 while its cathode is connected to 177 and the base of 172 and to resistor 175 and to the cathode of zener diode 178. The collector of 172 is connected to resistor 174, the anode of 178 and the gate of P-channel FET 171. The source of 171 is connected to 175 and its drain is connected to a negative power supply rail 170. Resistor 174 is also connected to 170. 171, 172, 173, 174, 175, 176, 177 and 178 form a negative linear regulator which defines the voltage floating negative rail voltage 101.

 

In order to minimise intrinsic delays of the amplifier 103, this should be a wide-band device. So to should 123, but the high frequency response of this device may be relaxed compared to 103 because 103 provides the basic high frequency transfer between 70 and 150 and 151, while 103 and 123 provide a low frequency path.

 

With reference to FIG. 2, the overall amplifier input is between 1 and ground 2. Resistor 3 connects 1 to resistor 4 and capacitor 5. 5 is also connected to ground 2 and acts as an r.f. block to input signals and is required to ensure overall amplifier stability. 4 is connected to the overall amplifier inverting input at the base of pnp transistor 6. Series resistors 15 and 16 connect the overall amplifier output 18 to said overall amplifier inverting input and this path is the overall amplifier's negative feedback path. A small valued capacitor 17 is connected between ground 2 and the node connecting 16 and 15. This is required for high frequency stability especially at high output currents at near voltage clipping levels. The overall amplifier non-inverting input at the base of pnp transistor 9 is connected to ground 2 via resistor 13, which is required for very high frequency stability.

 

Transistors 6 and 7 and 9 and 8 form a pair of complementary feedback pairs wired up as a first differential amplifier. The emitter of 6 is connected to the collector of 7 and resistor 10. The collector of 6 is connected to the base of 7 via a ferrite bead 80 required for very high frequency stability, and to resistor 83 which is also connected to a negative supply rail 36. The emitter of 9 is connected to the collector of 8 and resistor 11. The collector of 9 is connected to the base of 8 via a ferrite bead 81 required for very high frequency stability, and to resistor 84 which is also connected to the negative supply rail 36. Resistors 83 and 84 are of high value and so the current flowing though them is low and is effectively constant assuming that 36 is substantially more than 10 V. Resistor 10 and 11 are connected to each other and to their connection node, is connected a current source 12 fed from a positive power rail 14. The differential outputs of said first differential amplifier are at the emitters of 7 and 8. These each feed a series of cascode Darlington's consisting of transistors 20, 21, 22, 23, 26, 27, 28, 29. The emitter of 7 is connected to the emitter of 20 while the emitter of 8 is connected to the emitter of 22. The base input of the Darlington pair 20 and 21 is connected to the anode of zener diode 24 and decoupling capacitor 25 which is connected across 24. The cathode of 24 is connected to ground. The base input of the Darlington pair 22 and 23 is also connected to the anode of zener diode 24 which is connected to resistor 57.

 

The collectors of Darlington pair 20 and 21 are connected to the emitter of 26 and the collectors of Darlington pair 22 and 23 are connected to the emitter of 28. The base input of the Darlington pair 26 and 27 is connected to resistors 57 and 58, as too is the base input of the Darlington pair 28 and 29. The collectors of 26 and 27 are connected to resistor 30 and the non-inverting input of a third amplifier 34.

 

The negative supply to 34 is connected to supply rail 36 which is also connected to resistor 30 and resistor 33. The positive supply of 34 is connected to supply rail 35.

 

The output of 34 is connected to the base input of a Darlington pair of transistors 31 and 32. The emitter of 32 is connected to 33 and also to the inverting input of 34.

 

The emitter of 31 is connected to the base of 32 via a ferrite bead 82 which is required for stability purposes. The collectors of 28, 29, 31 and 32 are connected to the voltage amplification stage input 50, as is the overall amplifier dominant pole forming capacitor 75 and resistor 51. 58 is connected to the cathode of zener diode 56 which holds the voltage of a voltage reference rail 55. The anode of 56 is connected to supply rail 36. A decoupling capacitor 59 is connected across 56. The voltage across resistor 30 is faithfully reproduced across 33, assuming a high gain amplifier. Thus the current flowing through 30 is directly proportional to the current flowing through 33, which substantially equals the current flowing from the collectors of 31 and 32. Thus the current flowing from the collectors of 26 and 27 is in proportion to the current flowing out of the collectors of 31 and 32 according to the ratio of 30 to 33.

 

The high accuracy current mirror consisting of 30, 34, 31, 32, 33, 82 is owed to the local negative feedback loop. The local dominant pole is that intrinsic to amplifier 34.

 

50 is also connected to an inverting input of amplifier 52 via resistor 51. A non-inverting input of 52 is connected to 55. The supply to 52 is from rails 36 and 35 which is decoupled by capacitors 42, 60, 41 and 40. The output of 52 feeds resistor 62 which is also connected to resistors 63 and 67 and the emitter of transistor 65. 63 is connected to an inverting input of amplifier 64 which is also supplied from rails 35 and 36. The non-inverting input of 64 is connected to rail 55. Resistor 63 is only necessary if 64 is a "current feedback` operational amplifier. The output of 64 is connected to the input base of a Darlington pair of transistors 65 and 66. Variations in voltage at the output of 52 will be substantially proportional to variations in the output collector currents of transistors 65 and 66 owing to the local negative feedback loop of 63, 64, 65, 66. The node connecting 62, 63, 65 and 67 is a `virtual earth" at the potential of 55, assuming the voltage across 63 is negligible. Because of this and that the potential between 55 and 36 is constant, the current flowing through 67, which is thus connected across this potential, is constant. The collectors of 65 and 66 are connected to a cascode Darlington transistor pair 68 and 69 whose collectors in turn are collected to another cascode Darlington pair of transistors 83 and 84. The input base of this the 68/69 pair is connected to a node of divider chain consisting of resistors 71, 72 and 80 and dual series diode 82. This divider chain divides the voltage between the amplifier output 18 and rail 35. The collectors of 83 and 84 feed the output of the voltage amplification stage 70 and the input of the error corrected output stage. The amplifier overall dominant pole forming capacitor 75 is connected to 70.

 

Voltage variations at the output of 52 are thus in proportion to current variations at the output of collectors 83 and 84. The input base of this Darlington pair are connected to the node connecting 82 and 80. The inverting input of 52 is a "virtual earth" held at the potential of 55. A net output current from the collectors of 31, 32, 28 and 29 feeding into the voltage amplification stage at node 50 is fed to capacitor 75 and resistor 51. Assuming the gain of 52, 64, and Darlington's 65 and 66, 68 and 69, 83 and 84 is high, the current flowing into 51 will be very low owing to the local negative feedback and high input impedance of 52 and thus almost all the variable current flowing into the voltage amplifying stage will flow into 75. Assuming the input impedance of the error corrected output stage is reasonably high, the output voltage active variations at 70 will be accurately proportional to the integral of the net current variations from the collectors of 28, 29, 31 and 32. Thus the voltage amplification stage described herein forms a low distortion integrated input current to voltage converter. A local dominant pole is essential for local stability of the voltage amplification stage servo loop. This is implemented by the inclusion of a series capacitor 53 and resistor 54 connected between the output of 52 and the inverting input of 52. The values of 51, 53, 54, 62, 51 must be such that the closed loop gain of the voltage amplifier is stable.

 

Rail 35 voltage is set by the linear voltage regulator 38 whose input is connected to power rail 37 which is positive relative to 36. The "ground reference" of 38 is connected to 36 and the output to 35. Decoupling capacitor 39 is connected between 36 and 37.

 

The amplifier output is between 18 and ground 2. A resistor capacitor series network 74 and 73 is connected between 18 and ground 2 for stability purposes.

 

With reference to FIG. 3, three complementary identical parallel power output pairs are shown. One such pair consists of two buffer amplifiers 200 and 210, resistors 201, 202, 204, 205, 211, 212, 214, 215, an N-channel output FET source follower 203 and a P channel output FET source follower 213. The node 150 feeds and non-inverting input of 200. The supply to 200 is derived from the output signal rail 18 and the positive floating supply rail 100. The output of 200 is connected back to the inverting input of 200 via a resistor 201, which is only necessary if 200 is a "current feedback" operational amplifier. The output of 200 is connected to a resistor 202 which connects the gate of 203. The drain of 203 is connected to positive power rail 209 and its source is connected to the output signal rail 18 via parallel resistors 204 and 205. The node 151 feeds into the non-inverting input of amplifier 210. The supply to this amplifier is derived from the output signal rail 18 and the negative floating supply rail 101. The output of 210 is connected back to the inverting input of 210 via a resistor 211, which is only necessary if 210 is a "current feedback" operational amplifier. The output of 210 is connected to a resistor 212 which connects the gate of 213. The drain of 213 is connected to negative power rail 219 and its source is connected to the output signal rail 18 via parallel resistors 214 and 215. 200 and 210 may simply be a "buffer amplifiers." Decoupling capacitors 206 and 207 are connected between 209 and ground 2 and decoupling capacitors 216 and 217 are connected between 219 and ground 2. Decoupling capacitor 264 is connected between floating rail 100 and 18 and decoupling capacitor 271 is connected between floating rail 101 and 18.

 

This complementary pair of output transistors are simply source followers whose gates are supplied by buffers.

 

Any number of these stages may simply be connected in parallel as shown in FIG. 3, for example, where 3 such parallel pairs are shown. The role and connections of the following are identical: amplifiers 200, 220, 240, resistors 201, 221, 241, capacitors 264, 260, 262, resistors 202, 222, 242, N-channel power transistors 203, 223, 243, resistors 204, 205, 224, 225, 244, 245, amplifiers 210, 230, 250, resistors 211, 231, 251, capacitors 271, 273, 275, resistors 212, 232, 252, P channel transistors 213, 233, 253, resistors 214, 215, 234, 235, 254, 255, capacitors 206, 207, 226, 227, 246, 247 and capacitors 216, 217, 236, 237, 256, 257. The reason for the buffer associated with of each power transistor is that when many are used in parallel, the phase shift along the signal rails 150 and 151 relative to 18 at frequencies of the order of a MHz becomes highly significant with distance from 103, 121, 124 and 131 if these buffers are omitted, and 150 is connected directly to 202, 222 and 242, and 151 to 212, 232 and 252, but is not significant if the buffers are implemented assuming their input impedances and relatively high, and each buffer is in reasonably close proximity to its associated output transistor.

 

All the amplifiers employed in the local negative feedback loops and output transistor buffer amplifiers should be wideband devices for best results, namely 34, 52, 64, 103, 123, 200, 220, 240, 210, 230, 250. This is so that the closed loop phase shifts intrinsic to these devices is small at several MHz compared to the phase shifts associated with the local transistors within these local negative feedback paths whose non-linear characteristics are being corrected by these local negative feedback paths. Thus components external to these wideband amplifiers have values selected to maintain stability. The external components that a designer would select specifically for local negative feedback stability are 111, 110, 121, 124, 190, 125, 126, 51, 53, 54, and 62. It is also advantageous to employ wideband transistors, especially in the higher small current paths, namely 7, 8, 20, 22, 26, 28, 32, 65, 68, and 84 so that the phase shift of the overall amplifier at several MHz is dominated by the 90 degree phase shift of the voltage amplifier stage and the phase shift of the output transistors, assuming these are high power devices. This will enable a relative high degree of overall negative feedback and hence less distortion. It is also advantageous if these wideband devices have high gains and all the small signal transistors have low capacitance so that distortion arising from nonlinear capacitance is avoided. For integrated circuit operational amplifiers, wideband could be considered to be a gain bandwidth product of more than 100 MHz, high gain means an open loop gain of more than say 100 V/V, and a wideband transistor is a device with a transition frequency exceeding 500 MHz.

 

The dominant pole is defined by the overall amplifier open loop gain with all local negative feedback paths closed, and the valve of capacitor 75; the dominant pole forming capacitor.

 

FET voltage followers are chosen rather than power bipolar devices because of secondary breakdown considerations and because in class-B or AB, the cross-over distortion of bipolars will typically cause distortion substantially more than the performance cited above at 20 kHz.

[ASURA]

There has been considerable human effort into attaining low distortion in amplifiers of many applications at all frequencies. In 1950, the best audio power amplifiers produced distortion of about 0.1% at 1 kHz, and in the 1990s, this was reduced to about 0.001% at 1 kHz, and about 0.02% at 20 kHz, although one manufacturer claims 0.0025% at 20 kHz.

 

A majority of commercial audio power amplifiers more or less follow standard designs.

 

Details of some examples of these are given in a review by Douglas Self in a series of articles in "Electronics World+Wireless World" from August 1993 to January 1994, and also in his book, ISBN 0-7506-2788-3, "Audio power amplifier design handbook," Newness, reprinted 1997/8 and a second edition ISBN 0 7506 4527 X, also Newness, 2000. Another book containing a comprehensive review of amplifiers, is authored by Ben Duncan called "High performance Audio Power Amplifiers," Newness ISBN 0 7506 2629 1, 1996, reprinted 1997/8.

 

There are some exceptions to these designs: A Technics SE-A1 amplifier which is known of in some countries incorporates an A-class output stage supplied by a floating low voltage high current power supply. This power supply is connected to B-class High Voltage Output Stage.

 

An LT1166 integrated circuit is primarily intended to control quiescent bias feeding output transistors in audio amplifiers. The LT1166 consists of a low gain transconductance differential amplifier (gain of 0.125 mho) with an inverting and a non-inverting input. The circuitry has a local negative feedback path connecting an output of the power output stage to the inverting input of the transconductance amplifier. The input of the output stage is the non-inverting input of the transconductance amplifier. Two local dominant poles for stability are formed by the use of shunt capacitors to ground from the transconductance amplifier's outputs. This Linear Technology application circuitry promises distortions no less than many currently existing commercial products.

 

In Journal of Audio Engineering Society, vol. 29, no 1/2, January/February 1981, pages 27-30, M. J. Hawksford, discloses as a mere paper publication a theoretical means of cancelling distortion in any amplifier stage, including the output stage. This is achieved by subtracting the signals feeding the output power transistors inputs from the amplifier output, and then adding this signal back into the signal driving the output transistors' inputs.

 

Iwamatsu in U.S. Pat. No. 4,476,442 again as a mere paper publication disclosed circuitry based on the principles of Hawksford. In one embodiment, Iwamatsu discloses floating power supplies supplying the adding and subtracting circuitry. These floating supplies follow a voltage equal to the sum of the output signal plus a signal linearly proportional to the current flowing through the output load. However, Iwamatsu's circuits do not include local dominant poles.

 

Robert R. Cordell in "MOSPOWER APPLICATIONS," Siliconix Inc. ISBN 0-930519-0, 1984, 6.6.3 discloses an audio power amplifier essentially the same as one of the Hawksford's circuits, but including the essential local dominant poles required for stability. This circuit has no provision for thermal stability, nor floating power supply rails, which are rare in amplifiers.

 

The current inventor Bruce H Candy previously in U.S. Pat. No. 5,892,398 as a mere paper publication only, discloses an amplifier also utilizing the principles of Hawksford, but including local dominant poles required for stability, thermal tracking circuitry for thermal stability, floating power supplies which track the output signal, rather than to the sum of the output signal plus a signal linearly proportional to the current flowing through the output load as in the case of Iwamatsu. Candy also discloses an output stage input current source load which is also supplied by power form the floating power supplies. Candy claims that it is possible with this arrangement to attain a distortion of the order of 1 part per million at 20 kHz at several hundreds of watts output.

 

Williamson et al. in U.S. Pat. No. 5,396,194 describes as a mere paper publication a switch mode amplifier containing floating low voltage high current power supplies which supply an A-class amplifier. This is similar to the Technics SE-A1 except that the drive circuitry is switch-mode rather than class-B and that the power supplying the A-class amplifier is derived from the switch mode power supply rather than a separate power supply. All the claims are concerned with the switching power saving technique.

 

In one of the Williamson paper descriptions there was described floating power supplies to supply small signal operational amplifiers which are connected as servo loops to control the current flowing through the output devices. There are two feedback paths containing a capacitor which form two local dominant poles which are essential for stability.

 

The current inventor Bruce H Candy has considered an amplifier consisting of at least one operational amplifier, a first error correction amplifier, connected up as a servo loop to control the output voltage, as opposed to the output current as in the case of Williamson et al. These operational amplifiers would be supplied by power from floating power supplies which track the output voltage.

 

Candy further has considered a local dominant pole being required for stability, and the advantages of using wide-band operational amplifiers, with gain bandwidth products of more than 100 MHz. In addition, Candy has considered a second error correction amplifier, consisting of another operational amplifier, also preferably wide-band, connected up as a servo loop to control the output voltage stage which includes the first error correction amplifier. In other words, Candy has considered a 2nd order local dominant pole formed by the signal path being amplified by two error correction stages in series.

 

This also would be supplied by the floating power supplies. Further considered are the advantages of implementing high gain stages with local negative feedback and the attendant local dominant poles required for stability in other stages of the amplifier to reduce distortion. This arrangement does not require the precise setting of the adding and subtracting electronics disclosed by Hawksford and related circuits.

 

Audio power amplifiers usually consist of three definable stages: an input stage, voltage amplifier stage and output stage. Sometimes, the amplifier input stage and the voltage amplifier stage together are called the amplifier input stage. In power amplifiers, the output stage, sometimes called the power output stage, usually produces most distortion. However, the distortion of the power output stage may be substantially reduced by some of the concepts considered by me previously. Compared to these distortion reduced power output stages, the lowest distortion conventional input stages and voltage amplifier stages may produce substantially greater distortion. Conventional low distortion input stages are usually a differential voltage to current converter which produce a differential output current. In these low distortion traditional architectures, the differential current output of this input stage is connected to a current mirror, and the output node of the differential current output of the input stage and current mirror is connected to a common emitter cascode amplifier; the said common emitter amplifier sometimes being a Darlington. The amplifier's dominant pole is set by a network including a capacitor connected between the output and input of this common emitter cascode stage.

 

In his second edition, Douglas Self disclosed the advantages of a second order global dominant pole, consisting of splitting the integrating capacitor in the voltage amplification stage, that is the said dominant pole setting capacitor, and connecting a resistor between ground and the said common split capacitor node. This allows for more overall global feedback, and thus reduced distortion. However, this adversely affects the amplifier slew rate owing to lower loading impedance on the output of the voltage amplification stage.

 

Linear Technology describes in application note AN67 a "super gain block" small signal amplifier consisting of effectively a 5th order global dominant pole. This is claimed to have an open loop gain of 180 dB at 10 kHz.

 

An object of this invention is to provide improvements which assist in even more accurate amplification or at least, provides the public with a useful alternative. This has particular application to audio power amplifiers, herein defined to produce at least 5W into 8 ohms at least at audio frequencies.

 

DISCLOSURE OF THE INVENTION

 

In one form of this invention this can be said to reside in an electronic amplifier having an input, and an output, and including an output stage containing output transistors being connected to the electronic amplifier output, the electronic amplifier input being connected to an input stage, an output of the input stage being connected to an input of the output stage, wherein a global dominant pole is formed which, not taking into account effects of any output stage local dominant pole, is at least of third order, at least at audio frequencies and lower ultrasonic frequencies.

 

In preference the electronic amplifier includes within the input stage, at least two amplifiers, a first and second amplifier, wherein the electronic amplifier input is connected to an input of the first amplifier, and an output of the first amplifier is connected to an input of the second amplifier, and an output of the second amplifier is connected to an input of the output stage, wherein there are at least two local negative feedback paths, a first and second local negative feedback path, a first local negative path being between an output of the first amplifier and an input of the first amplifier, a second local negative path being between an output of the second amplifier and an input of the second amplifier, and an overall negative feedback path is connected between an input of the first amplifier and the output stage, wherein there is at least a third order global dominant pole, at least at audio frequencies, when effects of any output stage local dominant pole are not taken into account.

 

In preference, a first local negative feedback path forms at least a local dominant pole about the first amplifier, a first local dominant pole, and the second local negative path forms at least a local dominant pole about the second amplifier, a second local dominant pole, and the said first local dominant pole is at least first order and the said second local dominant pole is at least second order, at least at audio frequencies.

 

In preference, in the alternative, the said second local dominant pole is at least first order and the said first local dominant pole is at least second order, at least at audio frequencies.

 

In preference, the said second amplifier consists of two series connected amplifiers, a third and fourth amplifier, and the said second local negative feedback path is connected between an output of the fourth amplifier and the input of the said third amplifier, and a third local negative feedback path is connected between an output of the third amplifier and an input of the third amplifier.

 

In preference, the output stage includes an output error correction stage containing at least one amplifier, a fifth amplifier, an input to the output stage being connected to an input of the fifth amplifier, wherein there are at least two local negative feedback paths, a fifth and sixth local negative feedback path, a fifth local negative feedback path being between an output of the output stage and an input of the fifth amplifier and a sixth local negative path being between an output of the fifth amplifier and an input of the fifth amplifier, an output of the fifth amplifier is connected to an input of output stage transistor buffers or the output stage transistors, an output of output stage transistor buffers, if used, being connected to an input of the output transistors, wherein the circuit arrangement and values of the said fifth and sixth local negative feedback paths and fifth amplifier and output transistors and output transistor buffers are selected to contain at least a first order local dominant pole, a third local dominant pole, at least at audio frequencies.

 

In preference, at least one of the said first, second, third or fifth amplifier is a wideband differential operational amplifier with a gain-bandwidth product of greater than 100 MHz and direct current open loop differential voltage gain of more than 200V/V.

 

In preference, the fifth amplifier is supplied by power from a floating power supply means coupled to an output of the output stage so that a voltage of the floating power supply supplying the fifth amplifier will follow substantially an output voltage of the output stage when operational.

 

In preference, the said third local dominant pole is at least second order.

 

In preference, the electronic amplifier is capable of delivering at least 5 Watts output into 8 ohms at least at audio frequencies.

 

An advantage of the invention lies in the discovery that high order global dominant poles may also be implemented in audio power amplifiers, and that this may quite easily be implemented with the use of operational amplifiers, and this high order dominant pole may be distributed across both the voltage amplification stage and input stage, without adverse reduction in slew rate.

 

This allows for considerably more negative feedback at audio and ultrasonic frequencies, thereby enabling considerable reduction in distortion across the entire audio band and some of lower ultrasonic band.

 

Further aspects of the invention including the scope of the invention can be gained by reference to the following description and the claims.

 

For a better understanding of this invention it will now be described with reference to a preferred embodiment which is described hereinafter with reference to drawings as follows

 

BRIEF DESCRIPTION OF THE DRAWINGS

 

FIG. 1 shows a basic block diagram illustrating the location of the local and dominant pole forming networks in an amplifier.

 

FIG. 2 shows the input stage and voltage amplifying stage part of an amplifier with a 3rd order global dominant pole, with any output stage local dominant pole ignored.

 

FIG. 3 shows the error correction part of a second order local dominant pole error corrected output stage.

 

FIG. 4 shows the output buffers and output transistors of an output stage.

 

DESCRIPTION OF THE PREFERRED EMBODIMENT

 

With reference to FIG. 1, which shows a basic block diagram illustrating the location of the local and dominant pole forming networks in an amplifier:

 

An amplifier input is provided at 500 relative to earth 501. An amplifier output is provided between at 530 relative to earth 501. In this basic diagram, the amplifier output stage, which includes output transistors, is modelled very approximately by a first order low-pass filter consisting of resistor 526 and capacitor 527 connected to ground. The common node of 526 and 527 is connected to a unit gain buffer amplifier 525. The output of 525 provides the amplifier output 530. Overall negative feedback is provided by a resistor 531 connected between 530 and the overall amplifier inverting input 504, which is located at the non-inverting input of the differential amplifier 502. Resistor 503 is connected between 500 and 504.

 

A second order local dominant pole is provided in the local closed loop forward transfer of amplifier 502 by the local negative feedback network connected to 502 consisting of:

 

resistor 513 connected between ground 501 and the inverting input of 502,

 

series resistor 505 and capacitor 506 connected between the inverting input of 502 and a first node,

 

resistor 508 connected between the said first node and 501,

 

and capacitor 507 connected between the output of 502 and the said first node.

 

A first order local dominant pole is provided in the local closed loop forward transfer of differential amplifier 509 by the local negative feedback network connected to 509 consisting of:

 

resistor 510 connected between the output of 502 and the inverting input of 509,

 

series connected resistor 511 and capacitor 512 connected between the inverting input of 509 and the output of 509. The non-inverting input of 509 is connected to ground 501.

 

The output of 509 is connected to the input of an unity gain error corrected output stage, consisting of differential amplifier 520, buffer amplifier 525, resistors 519, 521, 524, 526 and capacitors 522, 523 and 527.

 

The forward transfer from 504 to the output of 509 forms a 3rd order local dominant pole; a second order in series with a first order. If the local dominant pole of the error corrected output stage is ignored, then this 3rd order local dominant pole provided by the closed loop forward transfer of 502 and 509 provides a 3rd order global dominant pole for the whole amplifier.

 

The mathematical forward transfer function in the frequency domain between 504 and the output of 509, assuming ideal components is

 

F1={1+R2/R1-1/(w2 C1R1C3R3)-j(1/(C1R1)+(1+R2/R1)/(C3R3))/w}{j/(wC4R4)-R5/R4} (1).

 

Here, the values of the components are as follows:

 

R1=513, R2=505, C1=506, R3=508, C3=507, R4=510, R5=511, C4=512, and w is the frequency in rads/S.

 

If say R1=R3=R4=R5=100 ohms, C1=C3=3.3 nF, C4=100 pF and R2=10 ohms, then at audio and ultrasonic frequencies, the forward transfer function is approximately

 

F1=-j/(w3 C1R1C3R3C4R4) (2).

 

Thus, at say 1 kHz, this is approximately 190 dB, and at 100 kHz, this is approximately 1003 times less (=120 dB less) or thus 70 dB.

 

In comparison, a typical 1st order amplifier, with a closed loop gain of the order of 30 dB, has at most a forward transfer gain of about 90 dB at 1 kHz (overall negative feedback path open), and 50 dB at 100 kHz. 100 kHz is the 5th harmonic of 20 kHz; traditionally the highest frequency measured in audio amplifier harmonic measurements.

 

As typical complementary voltage follower power MOSFET stages have useful responses up to a few MHz for unconditional stability, the forward transfer function (1) must be of the order of the amplifier closed loop gain at these frequencies. If the closed loop gain is of the order of 30 dB, the above values easily satisfy this criterion. If "video" or "wide-band" operational amplifiers and "wideband" transistors which are now of low cost and common, are implemented in circuitry within 502 and 509, these components will add little in terms of phase shift at a few MHz and thus will not intrinsically affect the stability criteria.

 

The error corrected output stage in FIG. 1 consists of differential operational amplifier 520, and the 1st order simulated output stage power transistors which consists of the unity gain buffer 525, and resistor 526 and capacitor 527. The time constant of the simulated low pass filter is the value of 526 multiplied by the value of 527 and in practice is of the order of 100 nS. 520 is wired up as a second order local dominant pole servo loop about the output stage, where resistor 521 is connected between the output 530 and inverting input of 520, series connected resistor 519 and capacitor 522 are connected between the inverting input of 520 and a second node, resistor 524 is connected between the output 530 and the said second node, and capacitor 523 is connected between the second node and the output of 520. The output of 520 is connected to the input of the low pass filter, namely resistor 526 which is connected to capacitor 527. The error corrected output stage input is at the non-inverting input of 520. The benefits of this 2nd order error corrected output stage have been described in my cited patents.

 

The forward transfer function of the whole "amplifier" in FIG. 1 is:

 

F2=(F1BG)/((B+jwt)(G+1)-F1B) (3)

 

Where G=the closed loop gain=(the value of 531)/(the value of 503), and

 

B=1+R7/R6-1/(w2 C6R6C8R8)-j(1/(C6R6)+(1+R7/R6)/(C8R8))/w

 

Here, the values of the components are as follows:

 

R6=521, R7=519, C6=522, R8=524, C8=523, and the value of the time constant of the value of resistor 526 multiplied by the value of 527 is t.

 

If R6=R7=R8=100 ohms, and C6=C8=2.2 nF, then the whole amplifier open loop gain in terms of breaking the amplifier closed loop at the input to the output transistors, say at the input to 525, with the amplifier input grounded is approximately

 

F3=1/((w5 C1R1C3R3C4R4C6R6C8R8)(G+1)) (4)

 

at audio and ultrasonic frequencies.

 

At 1 kHz F3=275 dB and at 20 kHz, F3=75 dB, where G=30. Note this is the negative feedback factor taking the amplifier gain into account unlike values for F1 above. For a traditional 1st order global dominant pole audio power amplifier, these values are at most of the order of 60 and 20 dB respectively.

 

It should be noted that F1 deceases with frequency at a rate of 18 dB per octave and F3 at 30 dB per octave. In this application, I define a global third order dominant pole in an audio amplifier to at least exhibit an open loop gain, with the local negative feedback path containing the pole forming networks closed, which approximately decreases at 18 dB per octave for at lease a few decades of the audio and ultrasonic bands. Similarly, a fifth order dominant pole exhibits an open loop gain with local negative feedback path containing the pole forming networks closed, which approximately decreases at 30 dB per octave for at lease a few decades of the audio and ultrasonic bands.

 

FIGS. 2, 3 and 4 show an example of a circuit diagram of an amplifier with a 5th order global dominant pole as measured with the closed loop opened at the output transistors. FIG. 2 shows the input stage and voltage amplifying stage part of an amplifier with a 3rd order global dominant pole, with any output stage local dominant pole ignored. FIG. 3 shows the error correction part of a second order local dominant pole error corrected output stage, and FIG. 4 shows the output buffers and output transistors of an output stage.

 

This example is of an asymmetric circuit relative to the positive and negative power supply rails. This is for simplicity, and the same basic description could equally be applied to more or fully symmetric circuitry.

 

With reference to FIG. 2: The amplifier input is applied at 302, relative to ground 301. Across this input is a capacitor 303. This ensures the input impedance is low in the MegaHertz range to ensure global negative feedback stability. Resistor 304 connects 302 to the overall amplifier inverting input at the non-inverting input of differential operational amplifier 309. The overall amplifier negative feedback resistor 306 is connected between this overall amplifier inverting input and the amplifier output 305.

 

A second order local dominant pole is provided in the local closed loop forward transfer of amplifier 309 by the local negative feedback network connected to 309 consisting of:

 

resistor 312 connected between ground 301 and the inverting input of 309,

 

series connected resistor 327 and capacitor 325 connected between the inverting input of 309 and a third node,

 

resistor 326 connected between the said third node and ground 301,

 

and capacitor 324 connected between the output of 309 and the said third node.

 

A first order local dominant pole is provided in the local closed loop forward transfer of the voltage amplifier stage consisting of differential operational amplifier 332, resistors 330, 331, 333, 348, 391, 361, 362, 382, 385, capacitors 351, 390, 363, 369, diodes 365, 366, 367, 368, reference diode 364, and transistors 346, 347, 360, 380, 381, 383 and 384. The input of the voltage amplification stage is connected to the output of the input stage at the output of 309. This voltage amplifier stage input is connected to 330 which is connected to the non-inverting input of 332. The output of 332 is connected to the input base of the Darlington connected transistor pair 347 and 346. The emitter of this Darlington connected transistor pair is connected to ground 301 via resistor 348. This emitter is also connected via a local negative feedback path to the inverting input of 332 via series connected capacitor 351 and resistor 333. Resistor 331 is connected between ground 301 and the inverting input of 332. The collectors of the Darlington connected transistor pair 347 and 346 are connected to the collector of 360 and the emitter of Darlington connected transistor pair 380 and 381. The emitter of 360 is connected to negative voltage supply rail 370 via resistor 361, and the base of 360 is connected to diodes 365 and 366 and capacitor 363 via resistor 362, which is implemented for high frequency stability purposes. Series connected diodes 365 and 364 are connected in parallel across capacitor 363, and 363 and 364 are connected to 370. Series connected diodes 366, 367 and 368 are connected between diode 365 and the input base of Darlington connected transistor pair 380 and 381. This base is a.c. coupled to 370 via capacitor 369. A constant current flows from 360 approximately equal to the voltage across 364 divided by the value of 361. The collectors of Darlington connected transistor pair 380 and 381 are connected to the emitter of Darlington connected transistor pair 383 and 384. Resistor 382 is connected between the input bases of Darlington connected transistor pair 380 and 381 and pair 383 and 384. Resistor 385 is connected between the input base of Darlington connected transistor pair 383 and 384 and the amplifier output 305. The collectors of Darlington connected transistor pair 383 and 384 is connected the output of the voltage amplification stage 386. Series connected capacitor 390 and resistor 391 is connected between 386 and the voltage amplification stage virtual earth input at the non-inverting input of 332. The forward 1st order dominant pole of the voltage amplifier stage is selected by the choice of 391 and 390. The local negative feedback path via resistor 333 and capacitor 351 sets the local servo loop dominant pole required for local closed loop stability.

 

309 and 332 are supplied by power rails 310 and 311 which are a.c. coupled to ground via capacitors 399 and 397.

 

The forward transfer function between the overall amplifier inverting input at the non-inverting input of 309 and the output of the voltage amplification stage at 386 is approximately given by equation (1) where the value of 312=R1, 327=R2, 325=C1, 326=R3, 324=C3, 330=R4, 391=R5, and 390=C4.

 

With reference to FIG. 3:

 

The input of the error corrected output stage is at 400, which is connected to 386. 400 is connected to the non-inverting input of differential operational amplifier 402.

 

A second order local dominant pole is provided in the local closed loop forward transfer of amplifier 402 by the local negative feedback network connected to 402 consisting of:

 

resistor 423 connected between the amplifier output 401, the same as 305, and the inverting input of 402,

 

series connected resistor 422 and capacitor 421 connected between the inverting input of 402 and a fourth node,

 

resistor 424 connected between the said fourth node and the amplifier output 401,

 

and capacitor 420 connected between the output of 402 and the said fourth node.

 

The quiescent current flowing through the cascode connected Darlington connected transistor pairs 380, 381, 383 and 384, is set by a constant current flowing from the collector of transistor 404 via ferrite bead 403, which may be required for high frequency stability. The emitter of 404 is connected to floating positive supply rail 406 via resistor 405. Resistor 442 is connected between 401 and the base of 404. Capacitor 409 a.c. couples the base of 404 to 406 and series connected resistor 408 and diode 407 is connected between 406 and the base of 404.

 

The output of 402 is connected to the inputs of the N-channel buffer driver amplifiers shown in FIG. 4 at 425, which is also connected to the non-inverting input of buffer amplifier 450. The inverting input of 450 is connected to it's output, which feeds the gate resistor 451 of N-channel FET 452 which is thermally connected to the output power FETs in FIG. 4. The drain of 452 is connected to positive power rail 453, which is a.c. coupled to ground via capacitor 471.

 

The output of 402 is also connected to the inputs of the P-channel buffer driver amplifiers shown in FIG. 4 at 433, which is also connected to a constant current source consisting of differential amplifier 429, resistors 428, 431, 423 and 430, and also the non-inverting input of buffer amplifier 454 via parallel connected capacitor 426 and resistor 427. The inverting input of 454 is connected to it's output, which feeds the gate resistor 455 of P-channel FET 456 which is thermally connected to the output power FETs in FIG. 4. The drain of 456 is connected to negative power rail 457, which is a.c. coupled to ground via capacitor 470.

 

The current flowing through 452 and 456, via their sources, passes through resistor 460, producing a voltage which is measured and amplified by the differential connected amplifier consisting of differential operational amplifier 461 and resistors 463, 462, 464 and 465. 463 is connected between the amplifier output 401 and the non-inverting input of 461. 462 is connected between the source of 452 and the non-inverting input of 461. 464 is connected between the source of 456 and the inverting input of 461, and 465 is connected between the inverting input of 461 and it's output. The output of 461 is connected to the inverting input of differential operational amplifier 440 via resistor 445. Series connected resistor 441 and capacitor 443 is connected between the output of 440 it's inverting input. The non-inverting input of 440 is connected to 401, and resistor 444 is connected between the inverting input of 440 and floating negative supply rail 410. The output of 440 is connected to the control input of the said constant current source consisting of differential amplifier 429, resistors 428, 431, 423 and 430, namely to 423. 428 is connected between 433 and floating negative supply rail 410. 430 is connected between 433 and the output of 429. 431 is connected between the output of 429 and it's inverting input. 423 is connected between the output of 440 and the inverting input of 429.

 

The differentially connected amplifier consisting of differential operational amplifier 461 and resistors 463, 462, 464 and 465,

 

and the said constant current source consisting of differential amplifier 429, resistors 428, 431, 423 and 430,

 

and the servo loop dominant pole setting amplifier consisting of differential amplifier 440, resistors 441, 444 and 445, and capacitor 443,

 

together with resistor 427, buffers 450 and 454, and FETs 452 and 456 and resistor 460, form a thermally tracking servo loop which sets the output power transistors quiescent current. This is selected by the choice of 445 and 444. The floating supply rails 406 and 410 track the output 401 and are a.c. coupled to it by capacitors 472, 473, 474 and 475. 402, 429 and 440 are supplied with power by 406 and 410, and 450 by 406 and 401, and 454 by 401 and 410.

 

With reference to FIG. 4, three complementary identical parallel power output pairs are shown. One such pair consists of two buffer amplifiers 200 and 210, resistors 201, 202, 204, 205, 211, 212, 214, 215, an N-channel output FET source follower 203 and a P-channel output FET source follower 213. The node 150, which is connected to 425, feeds and non-inverting input of 200. The supply to 200 is derived from the amplifier output 18, which is the same as 305 and 401, and the positive floating supply rail 100, which may be the same as 406. The output of 200 is connected back to the inverting input of 200 via a resistor 201, which is only necessary if 200 is a "current feedback" operational amplifier. The output of 200 is connected to a resistor which is connected to the gate of 203. The drain of 203 is connected to positive power rail 209 and its source is connected to the output 18 via parallel resistors 204 and 205. The node 151, which is connected to 433, feeds into the non-inverting input of amplifier 210. The supply to this amplifier is derived from the output 18 and the negative floating supply rail 101, which may be the same as 410. The output of 210 is connected back to the inverting input of 210 via a resistor 211, which is only necessary if 210 is a "current feedback" operational amplifier. The output of 210 is connected to a resistor which is connected the gate of 213. The drain of 213 is connected to negative power rail 219 and its source is connected to the output 18 via parallel resistors 214 and 215. 200 and 210 may simply be a "buffer amplifiers." Decoupling capacitors 206 and 207 are connected between 209 and ground 2 and decoupling capacitors 216 and 217 are connected between 219 and ground 2. Decoupling capacitor 264 is connected between floating rail 100 and 18 and decoupling capacitor 271 is connected between floating rail 101 and 18.

 

This complementary pair of output transistors are simply source followers whose gates are supplied by buffers.

 

Any number of these stages may simply be connected in parallel as shown in FIG. 3, for example, where 3 such parallel pairs are shown. The role and connections of the following are identical: amplifiers 200, 220, 240, resistors 201, 221, 241, capacitors 264, 260, 262, resistors 202, 222, 242, N-channel power transistors 203, 223, 243, resistors 204, 205, 224, 225, 244, 245, amplifiers 210, 230, 250, resistors 211, 231, 251, capacitors 271, 273, 275, resistors 212, 232, 252, P-channel transistors 213, 233, 253, resistors 214, 215, 234, 235, 254, 255, capacitors 206, 207, 226, 227, 246, 247 and capacitors 216, 217, 236, 237, 256, 257.

 

For integrated circuit operational amplifiers, "wideband" could be considered to be a gain bandwidth product of more than say 100 MHz, with an open loop gain of more than say 200V/V, and a "wideband" transistor is a device with a transition frequency exceeding say 500 MHz.

 

In accordance with the teaching of this invention, an amplifier has been built that produces distortion harmonics to a 20 kHz sinewave of the order of 100 parts per billion, that is, of the order of -140 dB at several hundred watts output power.